Peripheral Module Disable (PMD)
Peripheral Module Disable is a feature available in the PIC16F18877 family that enables the firmware to disable certain peripherals that are not needed or won't be needed. At startup or a reset recovery, all peripherals are enabled or "On" or out of reset by default. The power consumption at this point would be at its peak, and disabling the modules not being used would reduce power consumption.
The method provides the option to power down or power up the modules that have this feature individually. This is done by disabling the peripheral's corresponding bit. The enabling or disabling of a peripheral is not instantaneous and would require at least i full clock cycle for the peripheral to be disabled or enabled.
The deployed code would need to consider the device's operating characteristics for when the peripheral is powered down or then powered back up. The delay between the change in the peripheral's state and its being operational would need to be factored in, especially if the module is needed for a critical or time-sensitive application.
When reset, the MCU returns all devices to the default state of "ON" which powers up all peripherals.
PMD operationally puts the selected peripherals into a RESET low state. As per a device that is in reset LOW, the MCLR line has been pulled low preventing the device from executing any instructions. When the line returns high, the operation will resume.
When a device peripheral or module is disabled and then enabled, there are effects on the system. For legacy reasons, all modules are ON by default following any Reset.
Exercise care when implementing PMD as the peripheral and its associated registers may be impacted and this could result in reduced or nulled capacity of adjacent modules or modules that operate in tandem.
When the module is disabled, disabling has the following effect:
β’ All clock and control inputs to the module are suspended; there are no logic transitions and the module will not function. β’ The module is held in Reset. β’ Any SFRs become βunimplementedβ - Writing is disabled - Reading returns 00h β’ Module outputs are disabled; I/O goes to the next module according to pin priority
When the register bit is cleared, the module is reenabled and will be in its Reset state; SFR data will reflect the POR Reset values. Depending on the module, it may take up to one full instruction cycle for the module to become active. There should be no interaction with the module (e.g., writing to registers) for at least one instruction after it has been re-enabled.
When the peripheral is enabled, a full clock cycle may be required for some modules to be active again. This implies that the enabling of a peripheral:
- Incurrs an operational delay
- Will not be available immediately after enabling
- Checks may be required or a reinitialization of the peripheral to ensure that it retains previous settings.
The following items are to be considered when powering up or powering down a peripheral.
- Powering down a module requires that the control bit is cleared or set to 0
- Powering up a module requires that the control bit is set to 1
The basic code sample below assumes a function exists to test for the need for the UART. When needed its on and when not is disabled or in a RESET low state.
The logic is inverted here, so when needed its set to 0, and when not its 1.
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